1. Field of the Invention
The present invention relates to a field effect transistor using compound semiconductors and a method for producing the same. In particular, the present invention relates to a field effect transistor used in a compound semiconductor integrated circuit capable of operating at a high speed which is incorporated in communication apparatuses, computers or the like.
2. Description of the Related Art
In order to operate a field effect transistor (hereinafter, simply referred to as a "FET") using compound semiconductors such as GaAs with a high operation frequency, the gate length needs to be sufficiently short. Photolithography utilizing UV light is not typically suitable for forming a gate having a gate length of 0.5 .mu.m or less since such a photolithography method has a resolution of 0.4 .mu.m to 0.5 .mu.m. Therefore, in general, a photolithography method utilizing an electron beam (hereinafter, simply referred to as an "EB lithography"), which has a higher resolution, is used.
However, EB lithography has the problems of having a high apparatus cost and low throughput.
Thus, methods for producing an FET in which side walls are used to form a gate are proposed, for example, in Japanese Laid-Open Patent Publication No. 60-136263, Japanese Laid-Open Patent Publication No. 61-82482, Japanese Laid-Open Patent Publication No. 62-45184 and Japanese Laid-Open Patent Publication No. 1-251668.
Hereinafter, such a method will be described with reference to FIGS. 8A through 8H.
First, referring to FIG. 8A, a photoresist (not shown) is formed on a substrate 11. Then, a selective ion implantation is conducted using photolithography to form an n region 13 in the surface area of the substrate 11. A portion of the n region 13 will act as a channel region of an FET to be fabricated. Thereafter, an insulating film 14 (e.g., an SiN film) is deposited on the substrate 11 so as to cover the n region 13, for example, by a CVD (chemical vapor deposition) method.
A resist (not shown) having a prescribed pattern is formed on the insulating film 14 by photolithography as an etching mask. Then, as shown in FIG. 8B, the insulating film 14 is subjected to anisotropic dry etching such as RIE (reactive ion etching) using the above etching mask to form an insulating pattern 15 made of the insulating film 14.
Thereafter, as shown in FIG. 8C, a film 16 made of a material capable of being a gate electrode (e.g., WSi) is deposited (hereinafter, simply referred to as a "gate electrode film 16") on the substrate 11 so as to cover the insulating pattern 15.
Then, as shown in FIG. 8D, the gate electrode film 16 is subjected to anisotropic dry etching such as RIE without using an etching mask to remove the portions of the gate electrode film 16 other than the portion adjacent to the outer side surface of the insulating pattern 15. As a result, a side wall 17 made of the gate electrode film 16 is formed adjacent to the side surface of the insulating pattern 15.
As shown in FIG. 8E, the insulating pattern 15 is selectively removed, leaving a side wall gate 18 made of the gate electrode film 16.
Then, as shown in FIG. 8F, a photoresist 19 having a prescribed pattern is formed on the substrate 11 by photolithography. A selective ion implantation is conducted using the photo resist 19 and the side wall gate 18 as a mask to form n+regions 22. The n.sup.+ regions 22 have an increased dopant concentration and a larger thickness (depth) compared with the n region 13. The positional relationship between the n region 13 and the n.sup.+ regions 22 is determined in a self-alignment manner using the side wall gate 18 as a mask.
Thereafter, the photo resist 19 is removed. Then, as shown in FIG. 8G, an insulating film 23 made of, for example, SiO.sub.2 is deposited on the substrate 11 so as to cover the n.sup.+ regions 22 and the side wall gate 18. The ion-implanted regions are activated by annealing, using the insulating film 23 as a protection film 23. As a result, active regions of the FET are formed.
Then, as shown in FIG. 8H, a source electrode 24 and a drain electrode 25 are formed on the n.sup.+ regions (source and drain regions) 22, respectively, via contact holes provided in the insulating film 23. Thereafter, required wirings for the FET are formed, thereby completing the FET.
In the above-described method, photolithography is not used for forming the side wall gate 18 which acts as the gate electrode. The gate length is instead controlled by the thickness of the gate electrode film 16 which will constitute the side wall gate 18. Thus, the resolution of the photolithography has nothing to do with the setting of the gate length.
However, the above-described conventional method for producing FETs in which a side wall is used for forming a gate has the following problems:
First, an FET produced by the above-described method will only have a one-finger type gate electrode (i.e., a gate electrode with only one electrode finger) and FETs having a gate electrode of multi-finger type or dual-gate type are not produced. In the case of one-finger type gate electrodes, the width of the electrode finger needs to be widened to increase the drain current of the FET. As a result, the size of the chip is increased when integrating many such FETs.
Secondly, a portion of the n region 13 which is exposed after the removal of the gate electrode film 16 may be damaged due to the anisotropic dry etching conducted in the step of forming the side wall 17 (see FIG. 8D). If a drain region of an FET consists of such a damaged portion, a gate-drain breakdown voltage may be deteriorated.